module DCO(
	input					clk,                    //时钟源
	input					rst,                    //复位信号
	
	input					carryPulse,             //借位信号，相当于计数器上限-1
	input					subtractionPulse,       //进位信号，相当于计数器上限+1
	input					bothEdge,               //上升沿触发信号
	
	output	reg	  controlled_signal       //受控信号
);

parameter	C = 100;                                //分频系数
reg	[9:0]		count;                              //计数器
reg [9:0]		count_cnt;                          //计数器上限

always @ (posedge clk or negedge rst)       //计数器上限
begin
	if(!rst)
		count_cnt <= C;
	else if(carryPulse)
		count_cnt <= count_cnt - 1'b1;
	else if(subtractionPulse)
		count_cnt <= count_cnt + 1'b1;
	else
		count_cnt <= count_cnt;
end

always @ (posedge clk or negedge rst)       //计数器计数
begin
	if(!rst)
		count <= 'd0;
	else if(count >= count_cnt)
		count <= 'd0;
	else if(bothEdge)
	    count <= 'd0;
	else 
		count <= count + 1'b1;
end

always @ (posedge clk or negedge rst)       //脉冲实现
begin
	if(!rst)
		controlled_signal <= 1'd1;	
	else if(count < (count_cnt >> 1))
		controlled_signal <= 1'b1;
	else
		controlled_signal <= 1'b0;
end

endmodule

